Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon or an epitaxial layer formed thereon, bounding the active regions.
One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate and an oxide liner is thermally grown on the trench walls. The trench is then refilled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. The active region typically comprises source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween. The gate electrode controls the turn-on and turn-off of each transistor. The quality and thickness of the gate oxide are crucial to the performance of the finished device.
A typical method of trench formation comprises initially growing a pad oxide layer on the substrate, and depositing a barrier nitride layer thereon. A photoresist mask is then applied to define the trench areas. The exposed portions of the nitride layer are then etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the nitride layer.
Next, the substrate is oxidized to form an oxide liner on the walls and base of the trench to control the silicon-silicon dioxide interface quality. The trench is then refilled with an insulating material (or "trench fill"), such as silicon dioxide derived from tetraethyl orthosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP) using the barrier nitride layer as a polish stop. In subsequent operations, the nitride and pad oxide are stripped off, and a gate oxide layer is grown on the exposed silicon of the substrate.
Disadvantageously, the gate oxide layer typically does not grow uniformly; i.e., it tends to be thinner at the trench edges where the gate oxide growth rate is smaller there to the curvature of the trench edges. The gate oxide grows at a decreased rate at the trench edges because silicon at the trench edges has a different crystallographic orientation than silicon at the main surface of the substrate. As a result of gate oxide thinning at the trench edges, the subsequently deposited polysilicon overlaps the trench edges. This is shown in FIG. 1, illustrating the substrate 1, trench edges 1a, liner oxide 2, insulating material 3, gate oxide 4 and polysilicon 5. The overlap of polysilicon undesirably results in polysilicon remaining in the trench after etching to form the gates. This residual polysilicon, along with the thin gate oxide at the trench edges, increases the electric field strength at the trench edges, leading to breakdown of the gate oxide, thereby decreasing device reliability.
There exists a continuing need for shallow trench isolation methodology wherein the resulting gate oxide layer at the trench edges exhibits high reliability and prevents the polysilicon layer from overlapping the trench edges.